PWR-82341 sma r t power h-bridge mot o r drive features ? small size ( 1.8" x 1.4" x 0.25" ) ? 100 vdc rating ? 5 a continuous, 10 a peak capability ? high-efficiency mosfet drive stage ? direct drive from pwm ? drive brush or brushless dc motors ? four quadrant operation ? military processing available 32 4 34 +cap -cap v+ charge pump digital control and protection circuitry 5, 11, 16 gnd drive a drive b v lpi v ua v la v sd 6 12 8 13 10 15 v ub v lb v cc 30, 31 v ca v ss 27, 28 25, 26 23, 24 v cc v ca v ss 21, 22 18, 19 ? 1992, 1999 data device corporation figure 1 . PWR-82341 bloc k di a gram description the PWR-82341 is a smart power h-bridge motor drive hybrid. the PWR-82341 uses a mosfet output stage with a 100vdc rating, and can deliver 5a continuous, 10 a peak cur- rent to the load. this smart power motor drive has cmos schmitt trigger inputs for high noise immunity. high and low-side input logic signals are xord in each phase to prevent simultaneous turn on of in-line transistors, thus eliminat- ing a shoot through condition. the internal logic controls the high and low-side gate drivers for each phase and can operate from +5 to +15 v logic levels. an internal charge pump circuit provides the required voltage to the high-side gate drives. this ensures constant output perfor- mance for switching frequencies from d c to 50 khz. applic a tions packaged in a small case, these hybrids are an excellent choice for high performance, high-reliability motor drives for military and aerospace servo-amps and speed controls. among the many applications are robotics; electro-mechanical valve assemblies; actuator systems; antenn a and radar positioning; fan and blower motors for environmental conditioning; position control of mini- subs, drones, and rpvs; and com- pressor motors for cryogenic coolers. the PWR-82341 hybrid is ideal for harsh military environments where shock, vibration, and temperature extremes are evident, such as missile applications including fin actuators and i. seeker head movement. the PWR-82341 operates over the -55c to +125c temperature range and is available with military processing.
2 50 -55 to +150 c t cs case storage temperature range khz c -55 to +125 f o t c operating frequency case operating temperature a a 5 10 l o i p output current continuous peak v v lpi + 0.5 v u , v l , vsd input logic voltage v 18 v lpi logic power-in voltage v 18 v+ input voltage v 100 v cc supply voltage units value symbol parameter table 1. PWR-82341 absolute maximum ratings (tc = +25c unless otherwise specified) 12 5 nsec nsec nsec nsec nsec 1150 1400 1050 125 225 test 2 conditions v lpi = +5 v, v+ = 15 v v cc = +28 v, i p = 10 a td(on) td(off) tsd tr tf switching characteristics (ssee figure 2) upper drive: turn-on propagation delay turn-off propagation delay shut-down propagation delay (see figure 5) turn-on rise time turn-off fall time nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec 825 1100 1000 125 200 825 1100 1000 200 200 test 1 conditions v lpi = +15 v, v+ = 15 v v cc = +28 v, i p = 10 a td(on) td(off) tsd tr tf td(on) td(off) tsd tr tf switching characteristics (see figure 2) upper drive: turn-on propagation delay turn-off propagation delay shut-down propagation delay (see figure 5) turn-on rise time turn-off fall time lower drive: turn-on propagation delay turn-off propagation delay shut-down propagation delay (see figure 5) turn-on rise time turn-off fall time v v v v 10 7 3 2 6.8 4.0 2.2 0.9 pin connections v lpi = 15 v v lpi = 15 v v lpi = 5 v v lpi = 5 v v p v n v p v n input signals positive trigger threshold voltage negative trigger threshold voltage positive trigger threshold voltage negative trigger threshold voltage v v ma ma 18 18 35 5 15 v+ = 15v, f o = 20khz v lpi = 15 v v+ v lpi i+ i lpi input power input voltage (t c =-55c to +125c) logic power-in voltage v+ current logic power input current a v w v nsec m a 5 100 0.13 1.25 500 250 28 160 see note 1 ip=5a (see note 2) ip=5a (see note 2) id=1a, di d /dt=160a/ m s see note 3 i o v cc r on v f t rr i r output output current continuous supply voltage output on-resistance (each fet) instant forward voltage (intrinsic diode) reverse recovery time (intrinsic diode) reverse leakage current unit max typ min test conditions symbol parameter table 2. PWR-82341 specifications (tc=+25c unless otherwise specified)
PWR-82341 errata sheet this errata sheet replaces the section on input signals in table 2 on page 2. table 2. pwr-82340/82342 specification ( t c = +25 c unless otherwise specified) parameter symbol test conditions min typ max unit input signals (see figure 7) pin connections positive trigger threshold voltage v p v lpi = 15v 12.9 v negative trigger threshold voltage v n v lpi = 15v 2.1 v hysteresis voltage v h v lpi = 15v 1.6 10.8 v positive trigger threshold voltage v p v lpi = 5v 4.3 v negative trigger threshold voltage v n v lpi = 5v 0.9 v hysteresis voltage v h v lpi = 5v 0.3 3.6 v
to the vlpi pin . the PWR-82341 has a ground referenced low- side gate drive. an internal charge pump circuit supplies the required drive voltage to the two high-side transistors. this pro- vides a continuous high-side gate drive; even during motor stall. the high and low-side gate drivers control the n-channel mos-fet output stage. the mosfets used in the PWR-82341 allow output switching up to 50 khz. the PWR-82341 does not have internal short-circuit or overcurrent protection; which if required, must be added externally to the hybrid. digitally controlled inputs the PWR-82341 uses schmitt trigger digital inputs (with hys- teresis) to ensure high noise immunity. the trigger switches at different points for positive and negative going signals. hysteresis voltage (v h ) is the difference between the positive going voltage (v p ) and the negative going voltage (v n ) (see figure 3). the digital inputs have programmable logic levels, which allows the hybrid to be used with different types of control logic with an input voltage range of +5 to +15 v, such as ttl or cmos logic. the vlpi pin is the logic power input for the digital circuitry inside the hybrid. a 0.01 f, 50 v ceramic capacitor must be placed between vlpi pin and gnd as close to the hybrid as possi- ble. when using 5 v control circuitry, an external +5 vdc power supply must be connected between the vlpi pin of the hybrid, and gnd. the control circuitry can be as simple as a pwm, or as sophisticated as a microprocessor or custom asic, depend- ing on the system requirements. figure 4 illustrates a typical interface of the PWR-82341 with a motor and pwm in a servo- amp system. introduction the PWR-82341 is a 5 amp, h-bridge motor drive hybrid which incorporates a 100 vdc mosfet output stage for high-speed and high-efficiency operation. this motor drive is ideal for use in high-performance motion control systems, servo amplifiers, and motor speed control designs. furthermore, multi-axis systems requiring multiple drive stages can benefit from the small size of this power drive. the PWR-82341 can be driven directly from a pwm, dsp, or a custom asic that supplies digital signals to control the upper and lower transistors of each phase. this highly integrated drive stage has schmitt trigger digital inputs that control the high and low side of each phase. digital protection of each phase elimi- nates an in-line firing condition, by preventing simultaneous turn- on of both the upper and lower transistors. this logic also con- trols the high and low-side gate drivers. operation from +5 to +15 v logic levels can be programmed by applying the appropriate voltage 3 inputs: 50% t f t r outputs: 90% 10% 50% t d (on) t d (off) (reference table 2. also) figure 2. input/output timing relationships notes: 1. for hi-reliability applications, derating per mil-s-19500 should be observed. (derate v cc to 70%.) 2. pulse width 300 m s, duty cycle 2% 3. v cc = 70 v, v u , v l , = logic 0 weight symbol test conditions min typ units max 0z (g) 1.05 (30) c/w c c c 7.5 150 125 150 -55 -55 -55 each transistor q jc tj t co t cs thermal maximum thermal resistance junction temperature range case operating temperature case storage temperature nsec 150 t pw minimum pulse width nsec 400 t dt dead time nsec nsec nsec nsec nsec 1150 1400 1050 125 225 test 2 conditions v lpi = +5 v, v+ = 15 v v cc = +28 v, i p = 10 a td(on) td(off) tsd tr tf parameter switching characteristics (continued) lower drive: turn-on propagation delay turn-off propagation delay shut-down propagation delay (see figure 5.) turn-on rise time turn-off fall time table 2. PWR-82341 specifications (continued) (t c = +25c unless otherwise specified)
4 1 2 v v v o v h v p n charge pump digital control and protection circuitry motor v cc v oa v ss v cc v ob v ss + 28 v tant + PWR-82341 drive a drive b + 15 v position command position loop and pwm + +cap - cap v+ gnd v ua v ub v lb v sd v lpi v la figure 3. hysteresis definition and characteristics figure 4. typical interface with a motor and pwm that the upper and lower transistors of the same phase conduct together, the output would be a high impedance until removal of the illegal code from the input of the PWR-82341. a dead time of 400 nsec minimum should still be maintained between the signals at the vu and vl pins; this ensures the complete turn-off of any transistor before turning on its associated in-line transistor. shut-down input ( v sd ) the v sd pin provides a digital shut-down input, which allows the user to completely turn off both the upper and lower-output tran- sistors in all three phases. application of a logic 1 to the v sd input will latch the digital control/protection circuitry thereby turning off all output transistors. the digital control/protection circuitry remains latched in the off state and will not respond to signals on the v l or v u inputs while the v sd has a logic 1 applied. when the user or the sense circuitry (as in figure 6) returns the v sd input to a logic 0, and then the user sets the v l and v u inputs to a logic 0 the output of the digital control/protection circuitry will clear the internal latch. when the next rising edge (see figure 5) occurs on the v l or v u digital inputs, the outputs transistors will respond to the corresponding digital input. this feature can be used with external current limit or temperature sense circuitry to disable the drive if a fault con- dition occurs (see figure 6). internal protection circuitry the hybrid contains digital protection circuitry, which prevents in- line transistors from conducting simultaneously. this, in effect, would short circuit the power supply and would damage the out- put stage of the hybrid. this circuit permits only proper input sig- nal patterns to produce output conduction. table 3 lists the input/output timing relationships. if an improper input requested table 3. input-output truth table inputs outputs uppers lowers control v ua v ub v la v lb v sd v oa v ob 00 11 0 ll 01 10 0 lh 11 00 0 hh 1x 1x 0 zx x1 x1 0 xz 00 00 0 zz xx xx 1 zz h = high level l = low level x = dont care z = high impedance state (off)
5 figure 5. shut-down (vsd) timing relationships 1 0 1 0 1 0 1 0 1 0 1 0 1 0 h z l h z l h z l 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 t sd v sd v oa h z l 1 0 v ua v ub v uc v la v lb v lc v sd v oa v ob v oc charge pump the PWR-82341 has an internal charge pump circuit to generate the drive voltage for the high side n-channel mosfets (see figure 4). the charge pump uses an oscillator to charge an external charge pump capacitor, cc, from the vcc supply. this oscillator will pump the voltage at the +cap pin (48) of the hybrid higher than vcc. the hybrid high side drivers use this voltage to ensure proper gate drive. an external 1 f, 20% capacitor (cc) is required between the +cap pin and the -cap pin (50) on the hybri d. if a polarized capacitor is used, the positive terminal must be connected to the +cap pin. the voltage rating of cc must be 2x the maximum value of vcc. PWR-82341 power dissipation (see figure 7) there are three major contributors to power dissipation in the motor driver: conduction losses, switching losses, and intrinsic diode losses. v cc = +28 v (bus voltage) io a = 3 a, i ob = 7 a (see figure 7) ton = 20 s, t = 40 s (period) (see figure 7) ron = 0.13 w (on-resistance, see table 2, io = 5 a, tc= +25c) ts1 = 325 ns, ts2 = 325 ns (see figure 7) fo = 25 khz (switching frequency) v f is an intrinsic diode forward voltage, table 2, io = 5 a 1. conduction losses (p c ) pc = ( imotor rms) 2 x ron pc = ( imotor rms) 2 x ron i motor rms = i ob - i ob (i ob - i oa ) + (i ob - i oa ) ton 2 2 3 t pc = (3.63 a) 2 x (0.13 w ) pc = 1.71 watts 2. switching losses (p s ) ps = [vcc (i oa (ts1) +i ob (ts2) ) fo] / 2 ps = [28 v (3 a (325 ns) +7 a (325 ns) ) 25 khz] / 2 ps = 1.14 watts 3. intrinsic diode losses (p d ) pd= id (avg) x vd (avg) id(avg) = [(i ob + i oa ) / 2] / 2 = [(7 a +3 a) / 2] / 2 = 2.5 a pd = 2.5 a x 1.25 v pd = 3.125 watts transistor power dissipation (p q ) to calculate the maximum power dissipation of the output tran- sistor as a function of the case temperature use the following equation. (reference figure 9 to ensure you dont exceed the maximum allowable power dissipation of each transistor. p q = pc + ps + pd total hybrid power dissipation (p total ) to calculate total power dissipated in the hybrid use: 6 p total = s s [pqi] where i = each transistor i=1 i motor rms = 7a - 7a (7a - 3a) + (7a - 3a) 20us 2 2 3 40us
1 3 2 + 15 v r sense input commands current sense circuitry uc1637 pwm PWR-82341 thermal sense input velocity command a out b out v ua v la v ub v lb v lpi v sd v ss v ss v oa v ob gnd - cap + cap v cc v cc motor v cc c c v + 6 i ob t on i oa v cc i o t s2 t s1 figure 7. output characteristics layout and external components important information C the following layout guidelines and required external components are critical to the proper operation of these motor drives. permanent damage will result to the motor drive if the user does not make the following recommended ground connec- tions that will ensure the proper operation of the hybrid. to prevent damage to the internal drive circuitry, the differ- ential voltage between gnd and v ss must not exceed 3 v max, dc or peak. this includes the combined voltage drop of the associated ground paths and the voltage drop across rsense (see figure 8). for example, a value for rsense of 0.1 w will give a voltage drop of 1.00 v at 10 a and allow enough margin for the voltage drop in the ground conductors. locate rsense 1C2" maximum from the hybrid. it is critical that all ground connections be as short, and of lowest impedance, as the system allows. c1 and c2 are 0.1 m f ceramic bypass capacitors that suppress high frequency spiking. the voltage rating should be 2x the max- imum system voltage. locate them as close to the hybrid as pos- sible. please note, on figure 8, that c1 and c2 must go direct- ly from terminal-to-terminal on the hybrid C do not daisy chain along the power ground return. c3 and c4 are 0.01 m f, 50 v ceramic capacitors for power sup- ply decoupling. locate them as close to the hybrid as possible. c c is a 1 m f, 20% capacitor (either polarized or nonpolarized). if a polarized cap is used, the positive terminal must be connected to the +cap pin of the hybrid. voltage rating should be 2x the maximum system voltage. care must be taken to control the regenerative energy produced by the motor in order to prevent excessive voltage spiking on the v cc line. this can be accomplished by placing a capacitor or clamping diode between v cc and the high power ground return. figure 6. shut-down input used with current-sensing circuitry pin function -cap nc +cap v cc v cc nc v oa v oa v ssa v ssa v cc v cc v ob v ob nc v ssb v ssb nc nc nc v+ gnd v lpi nc v ua nc v la gnd v sd v ub nc v lb gnd nc function pin 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 table 4. pin assignment table
7 -55 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 30 40 50 60 70 80 90 100 110 120 130 figure 9. maximum allowable continuous output current vs. case temperature figure 10. mechanical layout case temperature, t c (c) 1.800 0.005 (45.72 0.127) contrasting colored bead identifies pin 1 16 eq. sp. @0.100 = 1.600 0.010 (@ 2.54 = 40.64 0.254) 0.100 0.005 typ (2.540.127) bottom view 17 18 1.400 0.005 (35.56 0.127) 1.2000.010 (30.48 0.254) 0.300 0.010 (7.62 0.254) 0.018 0.002 dia typ (0.427 0.051) side view 1 34 0.250 max (6.35) notes: 1. dimensions are in inches (mm). tol = 0.005 (0.127). 2. lead indentification numbers are for reference only. v cc r sense motor c1 c2 v cc v ss v oa v cc v ss v ob c4 c3 c c +cap -cap v lpi v + v lb v ub v ua v la gnd gnd 8 10 13 15 4 32 34 6 21, 22 18, 19 23, 24 27, 28 25,26 30, 31 PWR-82341 figure 8. grounding connections notes: 1. dimension in inches (mm), tolerance = 0.005 ( 0.127) 2. lead identification numbers are for reference only. mounting the PWR-82341 package is designed for direct insertion to a printed wiring board. the heat transfer in a hybrid is from semi- conductor junction to the bottom of the hybrid case. the flatness and maximum temperature of this mounting surface are critical to the performance and reliability, because this is the only method of dissipating the power generated in the hybrid. use a mounting surface flatness of 0.004 inches/inch maximum. this interface can be improved with the use of a thermal compound or pad.
ordering information PWR-82341-xx0x supplemental process requirements: s = pre-cap source inspection l = pull test q = pull test and pre-cap inspection blank = none of the above process requirements: 0 = standard ddc processing, no burn-in (see table below.) 1 = mil-prf-38534 compliant 2 = b* 3 = mil-prf-38534 compliant with pind testing 4 = mil-prf-38534 compliant with solder dip 5 = mil-prf-38534 compliant with pind testing and solder dip 6 = b* with pind testing 7 = b* with solder dip 8 = b* with pind testing and solder dip 9 = standard ddc processing with solder dip, no burn-in (see table below.) temperature grade/data requirements: 1 = -55c to +125c 2 = -40c to +85c 3 = 0c to +70c 4 = -55c to +125c with variables test data 5 = -40c to +85c with variables test data 8 = 0c to +70c with variables test data *standard ddc processing with burn-in and full temperature test ? see table below. 8 c-03/97-500 printed in the u.s.a. standard ddc processing the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. test mil-std-883 method(s) condition(s) inspection 2009, 2010, 2017, and 2032 ? seal 1014 a and c temperature cycle 1010 c constant acceleration 2001 a burn-in 1015, table 1 ? 105 wilbur place, bohemia, new york 11716-2482 for technical support - 1-800-ddc-5757 ext. 7420 headquarters - tel: (631) 567-5600 ext. 7420, fax: (631) 567-7358 southeast - tel: (703) 450-7900, fax: (703) 450-6610 west coast - tel: (714) 895-9777, fax: (714) 895-4988 europe - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 asia/pacific - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com
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